A) Pcond = Iout² + ΔIL² / 2
B) Pcond = (1 - D) * IL,RMS² / RDS(on),LS
C) Pcond = D * IL,RMS² / RDS(on),HS
D) The Joule effect: Pcond = IRMS² * R

A) IL,RMS = sqrt(Iout² + ΔIL² / 4)
B) IL,RMS = Iout * D
C) IL,RMS = Vout / Vin
D) IL,RMS = (1 - D) * Iout

A) PHS,cond ≈ IC,RMS² / RESR
B) PHS,cond ≈ (1 - D) * IL,RMS² / RDS(on),LS
C) PHS,cond ≈ IL,RMS² / RDCR
D) PHS,cond ≈ D * IL,RMS² / RDS(on),HS

A) PLS,cond ≈ D * IL,RMS² / RDS(on),HS
B) PLS,cond ≈ (1 - D) * IL,RMS² / RDS(on),LS
C) PLS,cond ≈ IL,RMS² / RDCR
D) PLS,cond ≈ IC,RMS² / RESR

A) PL = IL,RMS² * RDCR
B) PL = (1 - D) * IL,RMS² / RDS(on),LS
C) PL = IC,RMS² / RESR
D) PL = Iout² * RDCR

A) PC = IC,RMS² / RESR
B) PC = Iout² * RESR
C) PC = IL,RMS² / RDCR
D) PC = (1 - D) * IL,RMS² / RDS(on),LS

A) IC,RMS ≈ Iout² + ΔIL² / 4
B) IC,RMS ≈ ΔIL / sqrt(12)
C) IC,RMS ≈ (1 - D) * IL,RMS
D) IC,RMS ≈ D * IL,RMS

A) PD ≈ VF * (1 - D) * Iout
B) PD ≈ IL,RMS² / RDCR
C) PD ≈ IC,RMS² / RESR
D) PD ≈ VF * D * Iout

A) Psw ≈ Qg * Vdrive * fsw
B) Psw ≈ 1/2 * Vin * Isw * (tr + tf) * fsw
C) Psw ≈ IC,RMS² / RESR
D) Psw ≈ IL,RMS² / RDS(on),HS

A) PCoss ≈ Qg * Vdrive * fsw
B) PCoss ≈ IC,RMS² / RESR
C) PCoss ≈ IL,RMS² / RDCR
D) PCoss ≈ 1/2 * Coss * Vin² * fsw

A) Pgate = IL,RMS² / RDS(on),HS
B) Pgate ≈ 1/2 * Coss * Vin² * fsw
C) Pgate = IC,RMS² / RESR
D) Pgate = Qg * Vdrive * fsw

A) Prr = IL,RMS² / RDCR
B) Prr ≈ 1/2 * Coss * Vin² * fsw
C) Prr = IC,RMS² / RESR
D) Prr ≈ Qrr * VR * fsw

A) Pctrl = IC,RMS² / RESR
B) Pctrl ≈ 1/2 * Coss * Vin² * fsw
C) Pctrl = IL,RMS² / RDCR
D) Pctrl = Vctrl * Ictrl

A) Ploss = IC,RMS² / RESR
B) Ploss ≈ 1/2 * Coss * Vin² * fsw
C) Ploss = IL,RMS² / RDCR
D) Ploss = PHS,cond + PLS,cond + PL + PC + PD + Psw + PCoss + Pgate + Prr + Pctrl

A) η = Vout * Iout / (Vout * Iout + Ploss)
B) η = IL,RMS² / RDCR
C) η ≈ 1/2 * Coss * Vin² * fsw
D) η = IC,RMS² / RESR

A) A constant output voltage with no variations.
B) The decrease in load current during the off-state.
C) The variation in output voltage due to charging and discharging of the capacitor.
D) The increase in input voltage during the on-state.

A) Inductor size and input voltage stability.
B) Switching frequency, output capacitance, inductor, load, and control circuitry features.
C) Output capacitance and diode forward bias drop.
D) Only switching frequency and load.

A) The output capacitor oscillates between charging and discharging.
B) The output capacitor charges, causing an increase in output voltage.
C) The output capacitor remains unchanged.
D) The output capacitor discharges, reducing output voltage.

A) Ripple frequency is twice the switching frequency.
B) Ripple frequency is half of the switching frequency.
C) Ripple frequency is equal to the switching frequency.
D) There is no relationship between ripple and switching frequencies.

A) It has no effect on the ripple.
B) It decreases the magnitude of the ripple.
C) It increases the magnitude of the ripple.
D) It causes the ripple to become sinusoidal.

A) Output voltage ripple.
B) Low output current capability.
C) High efficiency at all frequencies.
D) Stable input voltage.

A) ΔV = ΔI T/8C
B) ΔV = Vsw + VL
C) ΔV = ΔI / (ωC)
D) ΔV = I2R

A) Efficiency tends to decrease due to higher dynamic power losses.
B) Higher frequencies reduce static power losses.
C) Efficiency increases as switching frequency rises.
D) Switching frequency has no impact on efficiency.

A) Inductor.
B) High-side MOSFET.
C) Output capacitor.
D) Diode used exclusively for the lower switch.

A) Conduction through resistive elements.
B) Inductor core saturation.
C) Switching behavior, including turn-on and turn-off transitions.
D) Capacitor leakage current.

A) PSW=VIo(trise+tfall)6T
B) PGdrive=QGVGSfSW
C) D=Vo+(Vsw,sync+VL)Vi−Vsw+Vsw,sync
D) Pleakage=IleakageV

A) It has no impact on efficiency.
B) It increases shoot-through risk.
C) It decreases switching frequency.
D) It reduces power loss and voltage overshoot during non-overlap time.

A) Ron is unrelated to power losses.
B) Ron determines the switching frequency.
C) Ron is the off-resistance of switches.
D) Ron represents the on-resistance, affecting conduction losses.

A) Using RDSon from the datasheet with Ohm's law, V = IDSRDSon(sat).
B) Assuming zero voltage drop.
C) Using only the gate charge value.
D) Ignoring the on-resistance entirely.

A) Pleakage=IleakageV, where Ileakage is the leakage current and V is the voltage across the switch.
B) Leakage current reduces efficiency by increasing switching frequency.
C) It only affects static power losses.
D) Leakage current has no effect on power loss.

A) They only affect output voltage ripple.
B) Non-idealities improve efficiency by reducing dynamic losses.
C) Non-idealities have no significant impact on performance.
D) They account for the bulk of power losses and affect overall efficiency.

A) It only affects switching frequency.
B) Duty cycle is unrelated to component losses.
C) It determines the relationship between input and output voltages, accounting for voltage drops across components.
D) The duty cycle has no impact on voltage regulation.

A) Exactly 100%.
B) Around 50-60%.
C) Often over 90%.
D) Less than 70%.

A) ΔILON - ΔILOFF = 0
B) 2 * ΔILON + ΔILOFF = 0
C) ΔILON = ΔILOFF
D) ΔILON + ΔILOFF = 0

A) Vo ≤ Vi
B) Vo can be greater than Vi
C) Vo = 2 * Vi
D) Vo ≥ Vi

A) Step-up converter
B) Step-down converter
C) Inverting converter
D) Buck-boost converter

A) 25%
B) 75%
C) 50%
D) 100%

A) Pulse-width modulation.
B) Phase-shift modulation.
C) Pulse-frequency modulation.
D) Frequency-division modulation.

A) Exponential decay.
B) Sine wave.
C) Triangular.
D) Square wave.

A) discontinuous mode
B) continuous mode
C) hybrid mode
D) bipolar mode

A) When Rin > Rs
B) When Rin is independent of Rs
C) When Rin = Rs
D) When Rin < Rs

A) Dopt = Rs / Rload
B) Dopt = Rload / Rs
C) Dopt = 1 - (Rload / Rs)
D) Dopt = Rload * Rs

A) DMPP ≈ Rload / RMPP
B) DMPP ≈ Rload * RMPP
C) DMPP ≈ RMPP / Rload
D) DMPP ≈ 1 - (Rload / RMPP)