A) FP6 B) SP3 C) AM4 D) sWRX8
A) DDR4-3200 in octa-channel mode B) DDR4-3200 in dual-channel mode C) DDR5 and LPDDR5 D) Eight-channel DDR4-3200
A) 512 KB B) 64 MiB C) 32 KB D) 64 KB (32 KB data + 32 KB instruction)
A) 512 KB B) 64 MiB C) 32 KB D) 64 KB
A) 128 B) 16 C) 64 D) 24
A) 4 B) 128 C) 16 D) 8
A) Includes AV1 hardware decoding iGPU B) No integrated graphics C) Includes integrated GCN 5th generation GPU D) Includes dual GPUs
A) TSMC 7FF B) TSMC N6 C) GloFo 14 nm D) TSMC N7 FinFET
A) AM4 B) sWRX8 C) FP6 D) SP3
A) DDR4-3200 in octa-channel mode B) Eight-channel DDR4-3200 C) DDR4-3200 in dual-channel mode D) DDR5 and LPDDR5
A) 24 B) 128 C) 8 D) 16
A) 4 B) 64 C) 16 D) 8
A) None B) AV1 hardware decoding GPU C) GCN 5th generation GPU D) RDNA GPU
A) FP6 B) SP3 C) AM4 D) sWRX8
A) DDR4-3200 or LPDDR4-4266 in dual-channel mode B) Eight-channel DDR4-3200 C) DDR5 and LPDDR5 D) DDR4-3200 in octa-channel mode
A) 64 B) 24 C) 16 D) 128
A) GloFo 14 nm B) TSMC 7FF C) TSMC N7 FinFET D) TSMC N6
A) Milan B) Cezanne C) Rembrandt D) Barceló
A) November 2021 B) March 15, 2021 C) January 2020 D) April 2022
A) FP6 socket B) AM4 socket C) SP3 socket D) sWRX8 socket
A) Zen 3 microarchitecture B) Zen 4 microarchitecture C) Zen 3+ microarchitecture D) Zen 2 microarchitecture
A) TSMC N6 process B) TSMC N7 FinFET C) TSMC 7 nm process D) GloFo 14 nm process
A) TSMC 7 nm process B) GloFo 14 nm process C) TSMC 7FF D) TSMC N6 process
A) Two B) Multiple C) Eight D) One
A) Dual-channel DDR4-3200 B) Eight-channel DDR4-3200 C) DDR5 and LPDDR5 D) Octa-channel DDR4-3200
A) 64 B) 32 C) 8 D) 128
A) AV1 hardware decoding B) Integrated GCN GPU C) GloFo 14 nm I/O die D) 64 MiB L3 cache dies (3D V-Cache)
A) Limited to octa-channel memory only B) Limited to uniprocessor operation (1P, single-socket) C) Limited to dual-processor operation (2P) D) Limited to 16 PCIe lanes
A) Milan B) Rembrandt C) Cezanne D) Zen 3+
A) April 2022 B) December 2022 C) March 15, 2021 D) January 2020
A) 128 B) 30 C) 16 D) 50
A) Up to 10% B) Up to 50% C) Up to 30% D) Up to 64%
A) IPC is 50% higher B) IPC is 30% higher C) IPC is identical to that of Zen 3 D) IPC is lower than Zen 3
A) TSMC 7FF node B) TSMC N7 FinFET node C) TSMC N6 node D) GloFo 14 nm node
A) Barceló B) Cezanne C) Rembrandt D) Milan
A) USB4 decoding B) AV1 hardware decoding C) 3D V-Cache decoding D) GCN 5th generation decoding
A) Early 2017 B) April 1, 2022 C) April 20, 2022 D) November 5, 2020
A) Milan B) Vermeer C) Raphael D) Matisse
A) 500 series B) 300 series C) 600 series D) 100 series
A) 25% B) 10% C) 19% D) 15%
A) DDR5 memory controller and new sockets B) Power efficiency and power management C) Integrated RDNA3 graphics D) Larger L2 cache and higher core counts
A) 16MB B) 64MB C) 128MB D) 32MB
A) 8 B) 2 C) 4 D) 1
A) 3D V-Cache B) Resizable BAR C) DirectStorage D) Infinity Fabric
A) 46 clock cycles B) 12 clock cycles C) 39 clock cycles D) 32 clock cycles
A) 39 cycles B) 64 cycles C) 46 cycles D) 12 cycles
A) 512KB B) 64MB C) 16MB D) 32MB
A) 12 cycles B) 46 cycles C) 4 cycles D) 39 cycles
A) 96MB B) 128MB C) 32MB D) 64MB
A) Ryzen 9 5950X B) Ryzen 7000X3D family C) Ryzen 6000 series D) Ryzen 5 5600X3D
A) DDR4 B) HBM2 C) DDR5 D) DDR3
A) AM5 B) AM4 C) SP5 D) sTRX8
A) Early 2017 B) November 5, 2020 C) April 1, 2022 D) 2019
A) Four two-core complexes B) Two four-core complexes C) Single eight-core complex D) One single-core complex
A) 8MB B) 32MB C) 64MB D) 16MB
A) 16MB B) 32MB C) 8MB D) 64MB
A) 256 entries B) 2048 entries C) 512 entries D) 1024 entries
A) 128-bit Variable Accelerated Execution Set B) 256-bit Vector AES instructions C) 64-bit Virtual Advanced Encryption Standard D) 32-bit Vector Arithmetic Execution System
A) Integer vector processing B) Broadcast TLB flushing C) Cache line invalidation D) Branch target prediction
A) Cache Enhancement Technology / Security State B) Core Execution Thread / System Security C) Control-flow Enforcement Technology / Shadow Stack D) Central Encryption Transfer / Safe Storage
A) 92 B) 180 C) 96 D) 192
A) 180 B) 224 C) 96 D) 92
A) 180 entries B) 96 entries C) 256 entries D) 192 entries
A) 92 entries B) 224 entries C) 192 entries D) 180 entries
A) 256 B) 224 C) 192 D) 96
A) 256 B) 180 C) 224 D) 92
A) 6 B) 4 C) 8 D) 10
A) DDR4-2400 B) DDR4-2667 C) DDR4-3200 D) DDR4-2933
A) DDR4-3200 B) DDR4-2133 C) DDR4-2933 D) DDR4-2667
A) Vermeer B) Warhol C) Pinnacle Ridge D) Raphael
A) Mid-2018 B) Mid-2023 C) Mid-2020 D) Mid-2021
A) Pinnacle Ridge B) Warhol C) Raphael D) Vermeer
A) A full redesign B) A brand new microarchitecture from scratch C) A modest architectural refresh D) A downgrade in core count
A) Raphael B) Warhol C) Vermeer D) Pinnacle Ridge
A) It was released as Ryzen 5000 B) It was delayed until 2024 C) It was cancelled by AMD D) It was outsourced to Intel
A) Global energy crisis B) Global chip shortage C) Raw material surplus D) Transportation strike
A) Exclusively in Europe B) Worldwide C) Only in North America D) Only in Taiwan
A) RDNA2 B) Navi C) RDNA1 D) Vega
A) AM4, AM5 B) FP5, FP6 C) FP7, FP7r2 D) TR4, sTRX4
A) Rembrandt-R B) Rembrandt-X C) Rembrandt-Plus D) Rembrandt-Refresh
A) November 2024 B) April 2022 C) January 2023 D) October 2025 |