Central processing unit - Quiz
A) Microprocessors B) Transistors C) Integrated circuits D) Magnetic core memory
A) 1960 B) 1955 C) 1965 D) 1964
A) Instruction set B) Assembly language C) Operating system D) Microprogram
A) Lower physical size B) Short switching time C) Simplified logic gates D) Higher voltage tolerance
A) Digital Equipment Corporation B) IBM C) Cray Inc D) Fujitsu Ltd
A) Quantum processors B) SIMD vector processors C) Multi-core processors D) RISC processors
A) High power usage B) Lack of memory C) Fragile components D) Incompatibility
A) Reduced programming complexity B) Lower cost of production C) Increased memory capacity D) Lower power consumption
A) IBM Power B) IBM PC C) IBM Blue Gene D) IBM zSeries
A) Tens of megahertz B) Tens of kilohertz C) Tens of gigahertz D) Hundreds of hertz
A) Main processor B) Memory controller C) Peripheral controller D) System bus
A) Managing I/O circuitry B) Fetching data from external memory C) Storing CPU modes D) Performing arithmetic and logic operations
A) Arithmetic–logic unit B) Graphics processing unit C) Control unit D) Registers
A) Fixed-program computers B) Vacuum-tube relays C) Discrete transistor mainframes D) Stored-program computers
A) It used the Harvard architecture B) It lacked a control unit C) It required physical rewiring for different tasks D) It was too small to function efficiently
A) John von Neumann B) John William Mauchly C) Konrad Zuse D) John Presper Eckert
A) Harvard architecture uses punched cards for all logic B) Von Neumann is only used in embedded applications C) Harvard separates storage for instructions and data D) Harvard uses less power
A) Logic gates and transistors B) Microprocessors and ICs C) Relays and vacuum tubes D) Semiconductors and caches
A) 1 kHz to 10 kHz B) 100 kHz to 4 MHz C) 10 MHz to 100 MHz D) 1 GHz to 4 GHz
A) ALU and registers B) Peripheral interfaces C) External main memory D) Graphics processing units
A) ENIAC B) Manchester Mark 1 C) Atmel AVR microcontroller D) EDVAC
A) The removal of registers B) The integrated circuit C) The use of relays D) The abandonment of logic units
A) Caches and instruction-level parallelism B) Punched paper tape C) Vacuum tube controllers D) External storage
A) ENIAC B) EDVAC C) Manchester Baby D) Harvard Mark I
A) NOR gates B) AND gates C) NAND gates D) XOR gates
A) Gemini Spacecraft B) Apollo Guidance Computer C) Lunar Module 1 D) Voyager Mission
A) System/390 B) System/350 C) System/380 D) System/370
A) PDP-8 B) PDP-7 C) PDP-10 D) PDP-11
A) A graphics card B) A portable laptop C) A smartphone processor D) A 32-bit mainframe computer
A) Ten or fewer B) Five hundred thousand C) A hundred or more D) Fifty
A) Intel B) Fairchild C) Datapoint D) IBM
A) Robert Noyce B) Gordon Moore C) Federico Faggin D) Lee Boysel
A) Early 1960s B) Early 1970s C) Late 1970s D) Mid 1980s
A) 4 B) 24 C) 100 D) 1000
A) 100 B) 10,000 C) Roughly 1000 D) 10
A) Intel 8080 B) Motorola 6800 C) Intel 4004 D) IBM 360
A) 1968 B) 1974 C) 1971 D) 1980
A) Intel 8086 B) Intel 4004 C) Intel 8080 D) MOS 6502
A) 1974 B) 1977 C) 1971 D) 1982
A) As discrete components B) As vacuum tubes C) As microprocessors D) As numerous small ICs on circuit boards
A) Registers B) Modules C) Cores D) Nodes
A) Decreased gate parasitic capacitance B) Lower clock rates C) Larger transistor size D) Increased power consumption
A) Newton's law B) Von Neumann's law C) Moore's law D) Ohm's law
A) 2016 B) 2020 C) 2000 D) 2010
A) Voltage drop B) Electromigration C) Magnetic interference D) Thermal expansion
A) Data corruption B) Overheating C) Subthreshold leakage D) Increased clock jitter
A) The pipeline process B) The instruction cycle C) The bootstrap sequence D) The memory map
A) The instruction decoder output B) The cache memory index C) The incremented value in the program counter D) The previous instruction's result
A) Classic RISC pipeline B) Dynamic neural networks C) Quantum processing units D) Analogue circuitry
A) In the opcode B) In the program counter C) In a flags register D) In the cache
A) Executing arithmetic operations B) Retrieving an instruction from program memory C) Converting instructions into control signals D) Updating the flags register
A) Memory controller B) Opcode indexer C) Address register D) Instruction pointer
A) The program counter B) The speed of the clock C) The amount of available RAM D) Instruction set architecture (ISA)
A) The opcode B) The program counter C) The flag register D) The immediate value
A) A binary decoder B) An immediate value C) A register address D) A microprogram
A) Execute B) Initialization C) Compilation D) Storage
A) User input B) Cache miss C) Interrupt signal D) Clock pulse
A) Arithmetic logic unit B) Floating-point unit C) Binary decoder D) System bus
A) Memory is cleared B) The instruction is fetched C) The sum appears at the output D) The program branches
A) Signals B) Operands C) Constants D) Registers
A) Microcontrollers B) Desktop computers C) Smartphone processors D) Server computers
A) L3 B) L1 C) L2 D) L4
A) TLB B) L1 C) L3 D) L2
A) Asynchronous circuits B) Analog circuits C) Synchronous circuits D) Clockless circuits
A) The CPU must wait on its slowest elements B) It uses less energy C) It is impossible to design D) It requires no clock signal
A) Electrical signal delays B) Hardware incompatibility C) Excessive memory usage D) Operating system crashes
A) Xbox 360 B) Nintendo Wii C) Sega Dreamcast D) PlayStation 3
A) Pentium B) AMULET C) PowerPC D) Intel Core
A) Sawtooth wave B) Square wave C) Triangle wave D) Sine wave
A) Convert binary to decimal numerals B) Increase total number of memory locations C) Increase the word size of the CPU D) Regulate on-demand voltage supply
A) 32 B) 8 C) 64 D) 256
A) Two cycles B) Four cycles C) Eight cycles D) One cycle
A) Data path width B) Voltage width C) Bit width D) Integer size
A) Exactly one B) Two C) Less than one D) Greater than one
A) Out-of-order execution B) Branch prediction C) Register renaming D) Transactional memory
A) P4 B) P6 C) P3 D) P5 Pentium
A) Out-of-order execution B) Speculative execution C) VLIW D) Branch prediction
A) SISD B) MISD C) MIMD D) SIMD
A) Synchronous multiprocessor B) Shared memory processing C) Symmetric multiprocessing D) Systemic memory parallelism
A) Software patching B) Additional hardware C) External disk caching D) Manual thread migration
A) Manual bus synchronization B) NUMA C) Single-core expansion D) Pipelined cache architecture
A) Chip-level multiprocessing B) Direct memory access C) Instruction stream migration D) Discrete board architecture
A) Direct memory access B) Superscalar execution C) Symmetric multiprocessing D) Multi-threading
A) 7 B) 2 C) 4 D) 3
A) SISD B) MISD C) MIMD D) SIMD
A) Word processing B) Database indexing C) Operating system kernels D) Multimedia applications
A) Web browsing B) Social media networking C) Scientific research D) Desktop publishing
A) Late 2000s B) Early 1980s C) Mid-1990s D) Mid-1970s
A) They lacked multimedia support B) They were integer-only C) They were incompatible with memory D) They consumed too much power
A) Basic B) MAX C) SSE D) MMX
A) VMX B) MMX C) MAX D) SSE
A) trace-cpu B) core-monitor C) hpc-tool D) perf
A) A cluster B) A host C) A virtual server D) A vCPU
A) VPS B) vCPU C) V-Core D) vC
A) Less than 10% B) Exactly 100% C) Nearly 200% D) Approximately 50%
A) Physical space constraints on the integrated circuit B) Modern software is optimized for single-core only C) The memory hierarchy becomes unstable D) Inter-core communication consumes processing speed
A) Low clock rate issues B) Memory leaks in the kernel C) Return-oriented programming exploits D) Excessive cache latency
A) A vCPU B) A resource pool C) A cluster D) A host
A) Rated speed testing labs B) Large cloud providers C) Home office environments D) Small component manufacturers
A) Other components B) Only the cloud software C) Nothing else can be overclocked D) Only the motherboard |
Created with That Quiz —
where a math practice test is always one click away.