A) F2 B) F3 C) F1
A) 1ΚΩ B) 220k C) 5k D) 10ΚΩ
A) 5V B) 1µF C) 10V D) 0V
A) 1 B) 2ns C) 3 D) 1ns
A) 100ms B) 5ms C) 10ms D) 20ms
A) .tran B) .op C) .meas D) Pulse
A) Using cursor differences in voltage vs. time plot B) transient analysis C) None of them
A) Exponential rise to steady state B) An exponential decay curve. C) Exponential rise
A) R-C B) R/C C) R x C D) C x R
A) 0Hz B) 1Hz C) 5Hz D) -1Hz
A) 100 B) 50 C) 10 D) 120
A) Highest frequency B) 1MHz C) Low frequency D) 2MHz
A) gain B) High frequency C) Bode plot D) Frequency
A) Half power point (0.707 of peak amplitude) B) half of its maximum power. C) Half point (0.70 of peak amplitude)
A) 220V B) 170 V peak C) 12V D) 120V
A) 100μF B) 10μF C) 1000μF D) 2200µF
A) Bridge configuration with four diodes B) Bridge configuration with two diodes C) Bridge rectifier
A) difference between the maximum and minimm voltage B) None of them C) Peak-to-peak voltage measurement
A) Input power x output power B) Output power / Input power × 100% C) Input power / output power x 100%
A) LT1001 B) LM741 C) LT101 D) LM1001
A) -15V B) 5V C) ±15V D) 15V
A) 11 B) 12 C) 10 D) 13
A) 2V sine wave B) All of the above C) 1 V peak sine wave D) 1V sine wave
A) Bandwidth B) Frequency at 3dB point from midband gain C) Frequency at -3dB point from midband gain D) Sine wave
A) 10ΚΩ B) 1ΚΩ C) 20ΚΩ D) 120Ω
A) Low Output Impedance B) High Input Impedance C) CMRR
A) 1ΚΩ B) 120 C) 220 D) 10ΚΩ
A) difference amplifier configuration B) Apply a common-mode signal C) Identical signals applied to both inputs
A) Output voltage / differential input voltage B) Connect the inputs C) Apply a small differential input Vd=V-V-VdV+ -V
A) 1kHz B) 10kHz C) drops by -3dB D) drops by 3dB
A) Swollen-key B) Sallen-Key C) VCVS filter topology
A) -90 Celsius B) 80 degrees C) -120 degrees D) -90 degrees
A) -40 dB/decade B) 4 dB/decade C) All of the above D) Filter order (n) or slope in dB/decade
A) 0.770 B) 0707 C) 0.707 D) 0.7777
A) ±15V B) 5V C) 15V D) 12V
A) 100Ω B) 2kΩ C) 1ΚΩ
A) 5V B) 15V C) 120V D) 12V
A) AIIoad / AVout B) AVout/Alload C) Power supply
A) Parallel sense resistor with feedback B) Power supply C) Series sense resistor with feedback
A) Phase-Shift Oscillator B) Colpitts Oscillator C) Clap Oscillator D) Wien bridge
A) RC time constant B) Period and frequency C) Frequency-selective componentsi
A) Use a frequency counter B) Amplitude stabilizer C) Use oscilloscope to see how the output frequency changes D) AGC circuit with thermistor
A) Use a frequency counter B) Long-term frequency drift measurement C) oscilloscope to see how the output frequency changes
A) Exponential amplitude growth to steady state B) Across the resistance C) Closed loop gain
A) 1kHz B) 100kHz C) 50KHz D) 15KHz
A) Voltage-Mode Control (VMC) B) negative feedback control C) PWM feedback control
A) (Pout/Pin) x 100% B) (Pin/Pout) x 100% C) Pout x Pin x 100%
A) Damping ration B) Output voltage settling time C) Output voltage not settling time
A) 100μΗ B) 1μΗ C) 10μΗ D) 1000μΗ
A) Tolerance Analysis B) Monte Carlo C) AC analysis D) transient analysis
A) Using . Meas command B) CAD C) Using Netlist D) Using.subckt definition
A) .op B) .meas C) .tran D) .param
A) Plain Text B) SPICE compatible text format C) SPICE compatible image format
A) Top down design B) Visual hierarchy C) Symbol creation with subcircuits D) All of the above
A) Minimum timestep = 100 of smallest time constant B) Maximum timestep = 1/100 of Highest time constant C) Maximum timestep = 1/100 of smallest time constant
A) min= 1e-9 B) .options C) min= 1-9 D) gmin=1e E) gmin = 1e-9
A) .param B) .TRAN C) .step D) .ic command with node voltages
A) Reltol B) abstol 1e-12 C) abstol D) Reltol 1e-12
A) Reduce increment size B) Modify gmin stepping C) Tighten Convergence Settings D) Refine the mesh
A) Left-click plot, export data as text B) Right-click plot, export data as text C) File Export command from the Plot Pane
A) Node2 B) V(node1)-V(node2) C) node1 D) .MEAS
A) .op B) .tran C) .param D) .meas tran rms RMS V(out)
A) .fft V(out) B) .AC C) .tran D) .op
A) .MEAS P_AVG AVG V(R1)*I(R1) B) .meas avg power = avg (V(n1)*I(R1)) C) .AC D) .param E) .tran
A) Prefix with functional description B) Press F4 or the “label net" C) Hierarchical prefix with functional description D) Comment Text for descriptive labels and Net Name Labels/Ports
A) Add comments B) SPICE directives with comments C) Rename the schematic D) using a text file to document
A) Dedicated folder for each individual circuit project B) Separate folders for each analysis type C) My Documents\LTspiceXVII
A) .measure B) Clarity, functionality, and portability C) ProjectName_CircuitType_Version
A) External Version Control System (VCS) B) use the .step param command C) Sequential backup with date stamps
A) Verification vs. Validation B) Systematic, multi-analysis comparison C) Systematic node voltage checking
A) SPICE Error Log and the Waveform Viewer B) Check for syntax and units C) Error log analysis and stepping
A) Cross-Verification B) Theoretical calculation comparison
A) Systematic process B) Progressive component addition
A) Comparison with datasheet specifications B) Comparison of simulation results against unknown datasheet parameters
A) 1uF B) 1000uF C) 100uF |