INTHDL final exam reviewer

1. Behavioral flow describes a digital system at what level?

A) A high level, using algorithms or procedural constructs
B) The layout level
C) The transistor level
D) The gate-instance level

2. Behavioral modeling specifies:

A) What the system does, not how it is built
B) The exact gate delays
C) How the system is physically built
D) The wiring between modules

3. Writing behavioral HDL is most similar to:

A) Wiring a breadboard
B) Placing and routing a chip
C) Drawing a schematic
D) Writing pseudocode or an algorithm

4. Which constructs are used in behavioral modeling?

A) assign statements only
B) always, if, case, for
C) wire declarations only
D) AND/OR gate instances only

5. Which row correctly gives the abstraction level of each modeling type?

A) Behavioral: Medium, Dataflow: High, Gate-level: Low
B) All three are High
C) Behavioral: Low, Dataflow: Medium, Gate-level: High
D) Behavioral: High, Dataflow: Medium, Gate-level: Low

6. Gate-level modeling focuses on:

A) Hardware structure
B) Algorithmic behavior
C) Data movement
D) Testbench stimulus

7. Dataflow modeling focuses on:

A) Hardware structure
B) Simulation time
C) Data movement
D) Algorithmic behavior

8. Which is an example construct of dataflow modeling?

A) initial
B) assign
C) always
D) case

9. The always @ construct introduces a block that executes:

A) Only when inputs change
B) Only once at the start
C) Only on the falling clock edge
D) Whenever a signal in its sensitivity list changes

10. Is always @ limited to input signals?

A) Yes, inputs and outputs only
B) No, it can respond to any input, output, or internal
C) Yes, clock signals only
D) Yes, inputs only

11. In always @(sensitivity_list), the sensitivity list defines:

A) The signals that trigger the block to execute
B) The reset value
C) The data types of the signals
D) The module’s ports

12. Which block type is level-sensitive?

A) always @(negedge reset)
B) always @(posedge clk)
C) initial begin
D) always @(a or b or c)

13. In modern Verilog, always @(*) does what?

A) Ignores all signals
B) Triggers only on clock edges
C) Runs only once
D) Automatically includes all right-hand-side signals in the sensitivity list

14. always @(posedge clk or negedge reset) with if (!reset) q <= 0; executes on:

A) Falling edge of clk or rising edge of reset
B) Any change in d
C) Rising edge of clk or falling edge of reset
D) Rising edge of both

15. Mixing edge-sensitive and level-sensitive signals in the same sensitivity list is:

A) Usually not good practice
B) The only way to model a counter
C) Required for all designs
D) Required for flip-flops

16. Which statement is correct?

A) Combinational logic uses always @(); sequential logic uses always @(posedge clk ...)
B) Both use initial blocks
C) Combinational logic uses always @(posedge clk); sequential logic uses always @()
D) Both must use assign

17. The initial block is executed:

A) Only once at the start of simulation
B) Only during synthesis
C) Whenever an input changes
D) On every clock edge

18. The initial construct is typically used for:

A) Describing flip-flops in hardware
B) Describing combinational multiplexers
C) Testbenches, setting initial values, and file operations
D) Declaring module ports

19. The initial block is:

A) Not synthesizable in most FPGA/ASIC flows
B) Triggered by posedge clk
C) Required in every module
D) Always synthesizable

20. In initial begin clk = 0; reset = 1; #10 reset = 0; end, reset becomes 0 after:

A) 1 time unit
B) 10 time units
C) It never changes
D) 0 time units

21. Why are multiple always @ blocks allowed in one module?

A) Only the last block is used
B) Each block must share the same sensitivity list
C) Hardware is inherently parallel, and each block models an independent circuit element
D) To make code run slower

22. How do multiple always @ blocks in a module execute?

A) Alternating on each clock
B) Concurrently, so you should not assume an order
C) Only the first one runs
D) One after another in the order written

23. Within a single always block, statements execute:

A) In random order
B) In parallel with each other
C) Only once
D) Sequentially, in the order written

24. In the counter example with separate always blocks, the second block (with always @(*) that checks count == 4'b1111) models:

A) The clock generator
B) The sequential counter register
C) The reset synchronizer
D) The combinational display/check logic

25. The FSM example with separate blocks uses how many always blocks?

A) Two
B) One
C) Four
D) Three

26. In that FSM, the next-state logic is modeled as:

A) A testbench using initial
B) Combinational logic using always @(*)
C) A memory unit
D) Sequential logic using posedge clk

27. In module behavioral_example, if (a & b) y = 1; else y = 0; behaves as:

A) NOT gate
B) AND gate
C) XOR gate
D) OR gate

28. The step-by-step structure of a behavioral module is:

A) Logic, always block, module declaration, sensitivity list
B) Always block, logic, sensitivity list, module declaration
C) Module declaration, always block, sensitivity list, logic implementation
D) Sensitivity list, module declaration, always block, logic

29. A combinational circuit’s output depends on:

A) The clock only
B) Stored values only
C) Current inputs and past states
D) Current inputs only

30. A combinational circuit has:

A) A clock input
B) Flip-flops
C) Latches
D) No memory element

31. Which pair correctly states the output relationship?

A) Combinational: f(inputs + past states); Sequential: f(inputs)
B) Combinational: f(inputs); Sequential: f(inputs + past states)
C) Both: f(inputs)
D) Both: f(past states only)

32. Which of the following is NOT a combinational circuit?

A) Decoder
B) Half adder
C) D flip-flop
D) Multiplexer

33. A half adder has which inputs and outputs?

A) Inputs: SUM, CARRY; Outputs: A, B
B) Inputs: A, B; Outputs: A_gt_B, A_eq_B
C) Inputs: A, B; Outputs: SUM, CARRY
D) Inputs: A, B, S; Output: Y

34. In a half adder, SUM equals:

A) A NAND B
B) A OR B
C) A AND B
D) A XOR B

35. In a half adder, CARRY equals:

A) A AND B
B) A XOR B
C) A OR B
D) NOT A

36. Which Verilog line correctly describes the half adder SUM?

A) assign SUM = A | B;
B) assign SUM = A & B;
C) assign SUM = ~A;
D) assign SUM = A ^ B;

37. For a half adder with A = 1 and B = 1:

A) SUM = 1, CARRY = 1
B) SUM = 0, CARRY = 0
C) SUM = 1, CARRY = 0
D) SUM = 0, CARRY = 1

38. The 2-to-1 multiplexer equation is:

A) Y = D0 + D1 + S
B) Y = (~S · D1) + (S · D0)
C) Y = (~S · D0) + (S · D1)
D) Y = (S · D0) + (~S · D1)

39. In assign Y = (S) ? D1 : D0; when S = 0, Y equals:

A) D0
B) S
C) 0
D) D1

40. In the same multiplexer, when S = 1, Y equals:

A) D1
B) ~D1
C) D0
D) 0

41. A practical application of MUX/DEMUX is:

A) Sorting circuits
B) Memory addressing
C) Digital calculators
D) Data routing in communication

42. How many outputs does the 4-bit comparator example have?

A) 3
B) 4
C) 1
D) 2

43. In the comparator, which statement gives A equal to B?

A) assign A_eq_B = (A == B);
B) assign A_eq_B = (A > B);
C) assign A_eq_B = A & B;
D) assign A_eq_B = (A < B);

44. If A = 4'b1010 and B = 4'b0110, which output is 1?

A) A_gt_B
B) A_lt_B
C) All of them
D) A_eq_B

45. A practical application of comparators is:

A) Sorting circuits and microcontrollers
B) Data routing
C) Memory addressing
D) Display drivers

46. In the 2-to-4 decoder, if A = 2'b01, then Y equals:

A) 4'b0010
B) 4'b0100
C) 4'b1000
D) 4'b0001

47. In the 2-to-4 decoder, if A = 2'b11, then Y equals:

A) 4'b0001
B) 4'b1000
C) 4'b0100
D) 4'b0010

48. n the decoder example, why is the output declared output reg [3:0] Y with always @(*)?

A) Because it is assigned inside a procedural block that responds to any input change
B) Because it is sequential logic
C) Because it needs a clock
D) Because it stores the previous state

49. Which assignment selects output Y[2] in the 2-to-4 decoder (data-flow version)?

A) assign Y[2] = A[1] & A[0];
B) assign Y[2] = ~A[1] & ~A[0];
C) assign Y[2] = A[1] & ~A[0];
D) assign Y[2] = ~A[1] & A[0];

50. A practical application of encoders/decoders is:

A) Sorting circuits
B) Digital calculators
C) Memory addressing and display drivers
D) Core of microprocessors

51. A practical application of adders/subtractors is:

A) Digital calculators and processors
B) Memory addressing
C) Sorting circuits
D) Data routing

52. ALUs are described as:

A) The core of microprocessors
B) A clock generator
C) A memory unit
D) A type of flip-flop

53. Which is NOT listed as a type of combinational circuit?

A) Half adder / full adder
B) Encoder
C) Shift register
D) Multiplexer

54. Which are used to represent combinational circuits?

A) Truth tables, Boolean expressions, and HDL (Verilog)
B) Layout masks
C) State diagrams only
D) Timing diagrams only

55. Sequential circuits have outputs that depend on:

A) Both current inputs and previous states
B) Reset only
C) The clock only
D) Current inputs only

56. Unlike combinational circuits, sequential circuits have:

A) Memory elements such as flip-flops or latches
B) No outputs
C) No inputs
D) Only AND gates

57. Which is NOT a basic element of sequential circuits?

A) Decoder
B) Flip-flops
C) Clock signal
D) Latches

58. A synchronous sequential circuit changes its state only with the occurrence of a ___ signal.

A) clock
B) data
C) enable
D) reset

59. An asynchronous sequential circuit changes its output immediately in response to ___ changes.

A) power
B) clock
C) input
D) state-register

60. In Verilog, the D flip-flop is described using always @(___ clk).

A) posedge
B) level
C) change
D) negedge

61. The statement Q <= D; uses which type of assignment?

A) Procedural continuous
B) Non-blocking
C) Continuous
D) Blocking

62. In module d_flip_flop, q is declared as output reg because:

A) It is an input
B) It is a constant
C) It is a clock
D) It is assigned inside an always block and stores a value

63. In d_flip_flop with always @(posedge clk or posedge reset), the reset is:

A) Active-low
B) Synchronous
C) Disabled
D) Asynchronous

64. In that module, when reset is high, q is:

A) Set to 0 regardless of the clock
B) Set to d
C) Held at its previous value
D) Set to 1

65. In the else branch (q <= d;), the value of d is stored in q:

A) Only during reset
B) On the positive clock edge when reset is not high
C) On the falling clock edge
D) Immediately whenever d changes

66. For the d_flip_flop with reset = 0, d = 1, and a rising clock edge, q becomes:

A) High impedance
B) 0
C) Unknown
D) 1

67. In the JK flip-flop, when J = 0 and K = 0, Q:

A) Toggles
B) Becomes 0
C) Becomes 1
D) Keeps its value (Q <= Q)

68. In the JK flip-flop, when J = 0 and K = 1, Q:

A) Becomes 1
B) Toggles
C) Keeps its value
D) Becomes 0

69. In the JK flip-flop, when J = 1 and K = 0, Q:

A) Becomes 1
B) Becomes 0
C) Toggles
D) Keeps its value

70. In the JK flip-flop, when J = K = 1, Q will ___ on each clock edge.

A) reset
B) toggle
C) hold
D) set

71. In case ({J,K}), the braces {J,K} perform:

A) Addition
B) Concatenation
C) Subtraction
D) Comparison

72. The Verilog keyword case is paired with ___ to indicate the end of all conditional options.

A) endmodule
B) endcase
C) endif
D) end

73. A T flip-flop can be derived from a JK flip-flop by tying J and K to logic ___.

A) X
B) Z
C) 1
D) 0

74. When Q <= ~Q; is executed inside a flip-flop, the output will ___.

A) set
B) hold
C) toggle
D) clear

75. In the Counter module, output reg [3:0] count; means a ___-bit register output.

A) 4
B) 3
C) 2
D) 8

76. count <= count + 1; increases the counter by ___ each clock pulse.

A) 4
B) 2
C) 0
D) 1

77. A 4-bit counter can count from 0000 up to ___ before rolling over to zero.

A) 1110
B) 0111
C) 1000
D) 1111

78. When a 4-bit counter is at 1111 and the next clock edge arrives (reset not active), the count becomes:

A) 10000
B) 0000
C) 1111
D) 0001

79. The asynchronous reset in the counter is activated when reset becomes ___, regardless of the clock.

A) high (1)
B) low
C) unknown
D) floating

80. The statement always @(posedge clk or posedge reset) triggers on the rising edge of:

A) reset only
B) clk only
C) data and clk
D) clk and reset

81. In Verilog, always @(state) defines a block that executes whenever the value of ___ changes.

A) out
B) reset
C) clk
D) state

82. Which is an application of sequential circuits?

A) Decoders only
B) Counters, timers, shift registers, FSMs, and memory units
C) Comparators only
D) Half adders only

83. A timing diagram of a sequential circuit shows the relationship among:

A) Gates and wires
B) Module names
C) Clock, input, and output signals
D) Power and ground

84. A timing diagram helps visualize:

A) Source code syntax
B) Flip-flop state transitions and propagation delays
C) Synthesis reports
D) Chip layout

85. In the shift register, the operator {Q[2:0], shift_in} performs a bitwise ___ operation.

A) concatenation
B) rotation
C) addition
D) replication

86. In Q <= {Q[2:0], shift_in}; the new shift_in bit enters at:

A) Q[2]
B) Q[0]
C) Q[1]
D) Q[3]

87. If Q = 4'b0101 and shift_in = 1, the next Q after a clock edge is:

A) 0010
B) 0101
C) 1011
D) 1010

88. A shift register can be used to convert serial data into ___ form.

A) analog
B) decimal
C) gray code
D) parallel

89. A finite state machine (FSM) is:

A) A mathematical model of computation based on states and transitions
B) A type of memory chip
C) A clock generator
D) A kind of adder

90. What are the two main types of FSM?

A) Mealy and Johnson
B) Moore and Gray
C) Moore and Mealy
D) Mealy and Boolean

91. In a Moore machine, the output depends only on the:

A) Clock
B) Input
C) State
D) Reset

92. In a Mealy machine, the output depends on:

A) The clock only
B) The reset only
C) The state only
D) The state and the input

93. In the Moore FSM with parameter S0=0, S1=1, S2=2, how many bits does reg [1:0] state provide?

A) 4
B) 3
C) 1
D) 2

94. In the Moore FSM, from state S0 with in = 1, the next state is:

A) S1
B) S2
C) Reset
D) S0

95. In the Moore FSM, from state S1 with in = 0, the next state is:

A) S0
B) S2
C) Undefined
D) S1

96. In the Moore FSM, out = 1 when the state is:

A) S0
B) S2
C) Never
D) S1

97. In the FSM with separate always blocks, the state register block is:

A) Combinational, using always @(*)
B) Not needed
C) A testbench using initial
D) Sequential, using always @(posedge clk or posedge reset)

98. In that FSM, when the current state is 2'b11, next_state is:

A) 2'b11
B) 2'b10
C) 2'b00
D) 2'b01

99. In that FSM, out = (state == 2'b11); makes out equal 1:

A) Only when in = 1
B) Only in state 2'b11
C) In every state
D) Only in state 2'b00

100. In the Sequence Detector (1011), out = (state == S4); means the sequence is detected when the FSM reaches the ___ state.

A) S2
B) S0
C) S4
D) S3

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