A) Pcond = D * IL,RMS² / RDS(on),HS
B) The Joule effect: Pcond = IRMS² * R
C) Pcond = (1 - D) * IL,RMS² / RDS(on),LS
D) Pcond = Iout² + ΔIL² / 2

A) IL,RMS = Iout * D
B) IL,RMS = (1 - D) * Iout
C) IL,RMS = sqrt(Iout² + ΔIL² / 4)
D) IL,RMS = Vout / Vin

A) PHS,cond ≈ IC,RMS² / RESR
B) PHS,cond ≈ (1 - D) * IL,RMS² / RDS(on),LS
C) PHS,cond ≈ D * IL,RMS² / RDS(on),HS
D) PHS,cond ≈ IL,RMS² / RDCR

A) PLS,cond ≈ IC,RMS² / RESR
B) PLS,cond ≈ (1 - D) * IL,RMS² / RDS(on),LS
C) PLS,cond ≈ IL,RMS² / RDCR
D) PLS,cond ≈ D * IL,RMS² / RDS(on),HS

A) PL = (1 - D) * IL,RMS² / RDS(on),LS
B) PL = IC,RMS² / RESR
C) PL = Iout² * RDCR
D) PL = IL,RMS² * RDCR

A) PC = IL,RMS² / RDCR
B) PC = (1 - D) * IL,RMS² / RDS(on),LS
C) PC = IC,RMS² / RESR
D) PC = Iout² * RESR

A) IC,RMS ≈ (1 - D) * IL,RMS
B) IC,RMS ≈ ΔIL / sqrt(12)
C) IC,RMS ≈ Iout² + ΔIL² / 4
D) IC,RMS ≈ D * IL,RMS

A) PD ≈ IL,RMS² / RDCR
B) PD ≈ VF * D * Iout
C) PD ≈ VF * (1 - D) * Iout
D) PD ≈ IC,RMS² / RESR

A) Psw ≈ 1/2 * Vin * Isw * (tr + tf) * fsw
B) Psw ≈ Qg * Vdrive * fsw
C) Psw ≈ IC,RMS² / RESR
D) Psw ≈ IL,RMS² / RDS(on),HS

A) PCoss ≈ 1/2 * Coss * Vin² * fsw
B) PCoss ≈ IL,RMS² / RDCR
C) PCoss ≈ IC,RMS² / RESR
D) PCoss ≈ Qg * Vdrive * fsw

A) Pgate = IL,RMS² / RDS(on),HS
B) Pgate = Qg * Vdrive * fsw
C) Pgate ≈ 1/2 * Coss * Vin² * fsw
D) Pgate = IC,RMS² / RESR

A) Prr ≈ 1/2 * Coss * Vin² * fsw
B) Prr ≈ Qrr * VR * fsw
C) Prr = IC,RMS² / RESR
D) Prr = IL,RMS² / RDCR

A) Pctrl ≈ 1/2 * Coss * Vin² * fsw
B) Pctrl = IC,RMS² / RESR
C) Pctrl = IL,RMS² / RDCR
D) Pctrl = Vctrl * Ictrl

A) Ploss = IC,RMS² / RESR
B) Ploss = PHS,cond + PLS,cond + PL + PC + PD + Psw + PCoss + Pgate + Prr + Pctrl
C) Ploss = IL,RMS² / RDCR
D) Ploss ≈ 1/2 * Coss * Vin² * fsw

A) η = IC,RMS² / RESR
B) η ≈ 1/2 * Coss * Vin² * fsw
C) η = Vout * Iout / (Vout * Iout + Ploss)
D) η = IL,RMS² / RDCR

A) The decrease in load current during the off-state.
B) The variation in output voltage due to charging and discharging of the capacitor.
C) The increase in input voltage during the on-state.
D) A constant output voltage with no variations.

A) Switching frequency, output capacitance, inductor, load, and control circuitry features.
B) Only switching frequency and load.
C) Output capacitance and diode forward bias drop.
D) Inductor size and input voltage stability.

A) The output capacitor oscillates between charging and discharging.
B) The output capacitor charges, causing an increase in output voltage.
C) The output capacitor discharges, reducing output voltage.
D) The output capacitor remains unchanged.

A) Ripple frequency is half of the switching frequency.
B) Ripple frequency is equal to the switching frequency.
C) There is no relationship between ripple and switching frequencies.
D) Ripple frequency is twice the switching frequency.

A) It decreases the magnitude of the ripple.
B) It causes the ripple to become sinusoidal.
C) It has no effect on the ripple.
D) It increases the magnitude of the ripple.

A) High efficiency at all frequencies.
B) Low output current capability.
C) Output voltage ripple.
D) Stable input voltage.

A) ΔV = ΔI / (ωC)
B) ΔV = Vsw + VL
C) ΔV = ΔI T/8C
D) ΔV = I2R

A) Efficiency tends to decrease due to higher dynamic power losses.
B) Higher frequencies reduce static power losses.
C) Switching frequency has no impact on efficiency.
D) Efficiency increases as switching frequency rises.

A) High-side MOSFET.
B) Output capacitor.
C) Inductor.
D) Diode used exclusively for the lower switch.

A) Switching behavior, including turn-on and turn-off transitions.
B) Capacitor leakage current.
C) Conduction through resistive elements.
D) Inductor core saturation.

A) Pleakage=IleakageV
B) PGdrive=QGVGSfSW
C) D=Vo+(Vsw,sync+VL)Vi−Vsw+Vsw,sync
D) PSW=VIo(trise+tfall)6T

A) It reduces power loss and voltage overshoot during non-overlap time.
B) It decreases switching frequency.
C) It has no impact on efficiency.
D) It increases shoot-through risk.

A) Ron represents the on-resistance, affecting conduction losses.
B) Ron is unrelated to power losses.
C) Ron is the off-resistance of switches.
D) Ron determines the switching frequency.

A) Ignoring the on-resistance entirely.
B) Assuming zero voltage drop.
C) Using only the gate charge value.
D) Using RDSon from the datasheet with Ohm's law, V = IDSRDSon(sat).

A) Pleakage=IleakageV, where Ileakage is the leakage current and V is the voltage across the switch.
B) Leakage current has no effect on power loss.
C) Leakage current reduces efficiency by increasing switching frequency.
D) It only affects static power losses.

A) Non-idealities improve efficiency by reducing dynamic losses.
B) Non-idealities have no significant impact on performance.
C) They only affect output voltage ripple.
D) They account for the bulk of power losses and affect overall efficiency.

A) It only affects switching frequency.
B) It determines the relationship between input and output voltages, accounting for voltage drops across components.
C) The duty cycle has no impact on voltage regulation.
D) Duty cycle is unrelated to component losses.

A) Exactly 100%.
B) Less than 70%.
C) Often over 90%.
D) Around 50-60%.

A) ΔILON - ΔILOFF = 0
B) ΔILON = ΔILOFF
C) 2 * ΔILON + ΔILOFF = 0
D) ΔILON + ΔILOFF = 0

A) Vo ≤ Vi
B) Vo ≥ Vi
C) Vo = 2 * Vi
D) Vo can be greater than Vi

A) Buck-boost converter
B) Step-down converter
C) Inverting converter
D) Step-up converter

A) 50%
B) 25%
C) 100%
D) 75%

A) Phase-shift modulation.
B) Pulse-width modulation.
C) Frequency-division modulation.
D) Pulse-frequency modulation.

A) Square wave.
B) Triangular.
C) Exponential decay.
D) Sine wave.

A) discontinuous mode
B) continuous mode
C) bipolar mode
D) hybrid mode

A) When Rin < Rs
B) When Rin > Rs
C) When Rin is independent of Rs
D) When Rin = Rs

A) Dopt = 1 - (Rload / Rs)
B) Dopt = Rload / Rs
C) Dopt = Rload * Rs
D) Dopt = Rs / Rload

A) DMPP ≈ Rload * RMPP
B) DMPP ≈ RMPP / Rload
C) DMPP ≈ 1 - (Rload / RMPP)
D) DMPP ≈ Rload / RMPP