A) AM4 B) sWRX8 C) SP3 D) FP6
A) Eight-channel DDR4-3200 B) DDR4-3200 in octa-channel mode C) DDR5 and LPDDR5 D) DDR4-3200 in dual-channel mode
A) 32 KB B) 64 KB (32 KB data + 32 KB instruction) C) 512 KB D) 64 MiB
A) 512 KB B) 64 KB C) 64 MiB D) 32 KB
A) 64 B) 128 C) 24 D) 16
A) 128 B) 4 C) 8 D) 16
A) Includes dual GPUs B) Includes AV1 hardware decoding iGPU C) Includes integrated GCN 5th generation GPU D) No integrated graphics
A) GloFo 14 nm B) TSMC N7 FinFET C) TSMC 7FF D) TSMC N6
A) FP6 B) sWRX8 C) SP3 D) AM4
A) Eight-channel DDR4-3200 B) DDR4-3200 in octa-channel mode C) DDR5 and LPDDR5 D) DDR4-3200 in dual-channel mode
A) 16 B) 8 C) 128 D) 24
A) 8 B) 16 C) 64 D) 4
A) RDNA GPU B) AV1 hardware decoding GPU C) None D) GCN 5th generation GPU
A) SP3 B) FP6 C) AM4 D) sWRX8
A) DDR4-3200 or LPDDR4-4266 in dual-channel mode B) Eight-channel DDR4-3200 C) DDR5 and LPDDR5 D) DDR4-3200 in octa-channel mode
A) 24 B) 64 C) 128 D) 16
A) TSMC 7FF B) TSMC N6 C) GloFo 14 nm D) TSMC N7 FinFET
A) Rembrandt B) Cezanne C) Milan D) Barceló
A) January 2020 B) November 2021 C) April 2022 D) March 15, 2021
A) SP3 socket B) FP6 socket C) AM4 socket D) sWRX8 socket
A) Zen 3 microarchitecture B) Zen 4 microarchitecture C) Zen 2 microarchitecture D) Zen 3+ microarchitecture
A) TSMC 7 nm process B) TSMC N6 process C) TSMC N7 FinFET D) GloFo 14 nm process
A) TSMC 7 nm process B) TSMC 7FF C) GloFo 14 nm process D) TSMC N6 process
A) Two B) Eight C) One D) Multiple
A) Octa-channel DDR4-3200 B) Eight-channel DDR4-3200 C) DDR5 and LPDDR5 D) Dual-channel DDR4-3200
A) 32 B) 128 C) 8 D) 64
A) 64 MiB L3 cache dies (3D V-Cache) B) AV1 hardware decoding C) GloFo 14 nm I/O die D) Integrated GCN GPU
A) Limited to octa-channel memory only B) Limited to uniprocessor operation (1P, single-socket) C) Limited to 16 PCIe lanes D) Limited to dual-processor operation (2P)
A) Zen 3+ B) Cezanne C) Milan D) Rembrandt
A) December 2022 B) March 15, 2021 C) April 2022 D) January 2020
A) 50 B) 128 C) 30 D) 16
A) Up to 50% B) Up to 10% C) Up to 64% D) Up to 30%
A) IPC is 30% higher B) IPC is 50% higher C) IPC is lower than Zen 3 D) IPC is identical to that of Zen 3
A) GloFo 14 nm node B) TSMC 7FF node C) TSMC N7 FinFET node D) TSMC N6 node
A) Cezanne B) Barceló C) Rembrandt D) Milan
A) 3D V-Cache decoding B) AV1 hardware decoding C) GCN 5th generation decoding D) USB4 decoding
A) November 5, 2020 B) April 20, 2022 C) Early 2017 D) April 1, 2022
A) Raphael B) Matisse C) Vermeer D) Milan
A) 300 series B) 600 series C) 500 series D) 100 series
A) 15% B) 25% C) 19% D) 10%
A) DDR5 memory controller and new sockets B) Integrated RDNA3 graphics C) Power efficiency and power management D) Larger L2 cache and higher core counts
A) 32MB B) 16MB C) 128MB D) 64MB
A) 1 B) 2 C) 8 D) 4
A) Resizable BAR B) Infinity Fabric C) DirectStorage D) 3D V-Cache
A) 32 clock cycles B) 12 clock cycles C) 39 clock cycles D) 46 clock cycles
A) 46 cycles B) 39 cycles C) 64 cycles D) 12 cycles
A) 64MB B) 512KB C) 32MB D) 16MB
A) 12 cycles B) 39 cycles C) 46 cycles D) 4 cycles
A) 128MB B) 96MB C) 32MB D) 64MB
A) Ryzen 6000 series B) Ryzen 9 5950X C) Ryzen 7000X3D family D) Ryzen 5 5600X3D
A) DDR4 B) DDR3 C) HBM2 D) DDR5
A) sTRX8 B) SP5 C) AM5 D) AM4
A) November 5, 2020 B) April 1, 2022 C) Early 2017 D) 2019
A) One single-core complex B) Four two-core complexes C) Two four-core complexes D) Single eight-core complex
A) 64MB B) 32MB C) 16MB D) 8MB
A) 64MB B) 16MB C) 8MB D) 32MB
A) 256 entries B) 512 entries C) 1024 entries D) 2048 entries
A) 256-bit Vector AES instructions B) 64-bit Virtual Advanced Encryption Standard C) 128-bit Variable Accelerated Execution Set D) 32-bit Vector Arithmetic Execution System
A) Integer vector processing B) Broadcast TLB flushing C) Cache line invalidation D) Branch target prediction
A) Control-flow Enforcement Technology / Shadow Stack B) Core Execution Thread / System Security C) Cache Enhancement Technology / Security State D) Central Encryption Transfer / Safe Storage
A) 192 B) 180 C) 92 D) 96
A) 96 B) 92 C) 224 D) 180
A) 256 entries B) 180 entries C) 96 entries D) 192 entries
A) 92 entries B) 192 entries C) 224 entries D) 180 entries
A) 224 B) 256 C) 96 D) 192
A) 180 B) 224 C) 256 D) 92
A) 8 B) 10 C) 4 D) 6
A) DDR4-3200 B) DDR4-2400 C) DDR4-2667 D) DDR4-2933
A) DDR4-2933 B) DDR4-3200 C) DDR4-2133 D) DDR4-2667
A) Warhol B) Vermeer C) Pinnacle Ridge D) Raphael
A) Mid-2023 B) Mid-2020 C) Mid-2018 D) Mid-2021
A) Raphael B) Warhol C) Pinnacle Ridge D) Vermeer
A) A brand new microarchitecture from scratch B) A modest architectural refresh C) A downgrade in core count D) A full redesign
A) Pinnacle Ridge B) Vermeer C) Warhol D) Raphael
A) It was delayed until 2024 B) It was released as Ryzen 5000 C) It was outsourced to Intel D) It was cancelled by AMD
A) Transportation strike B) Raw material surplus C) Global energy crisis D) Global chip shortage
A) Only in North America B) Only in Taiwan C) Worldwide D) Exclusively in Europe
A) RDNA1 B) Navi C) Vega D) RDNA2
A) FP5, FP6 B) AM4, AM5 C) TR4, sTRX4 D) FP7, FP7r2
A) Rembrandt-X B) Rembrandt-Plus C) Rembrandt-Refresh D) Rembrandt-R
A) October 2025 B) November 2024 C) January 2023 D) April 2022 |