A) Microprocessors B) Magnetic core memory C) Integrated circuits D) Transistors
A) 1960 B) 1964 C) 1955 D) 1965
A) Assembly language B) Instruction set C) Microprogram D) Operating system
A) Simplified logic gates B) Higher voltage tolerance C) Short switching time D) Lower physical size
A) Fujitsu Ltd B) IBM C) Cray Inc D) Digital Equipment Corporation
A) RISC processors B) Quantum processors C) Multi-core processors D) SIMD vector processors
A) Lack of memory B) Fragile components C) Incompatibility D) High power usage
A) Reduced programming complexity B) Lower power consumption C) Increased memory capacity D) Lower cost of production
A) IBM zSeries B) IBM Power C) IBM PC D) IBM Blue Gene
A) Hundreds of hertz B) Tens of gigahertz C) Tens of megahertz D) Tens of kilohertz
A) Memory controller B) Peripheral controller C) Main processor D) System bus
A) Managing I/O circuitry B) Storing CPU modes C) Performing arithmetic and logic operations D) Fetching data from external memory
A) Arithmetic–logic unit B) Control unit C) Registers D) Graphics processing unit
A) Stored-program computers B) Fixed-program computers C) Vacuum-tube relays D) Discrete transistor mainframes
A) It required physical rewiring for different tasks B) It was too small to function efficiently C) It used the Harvard architecture D) It lacked a control unit
A) John von Neumann B) John Presper Eckert C) Konrad Zuse D) John William Mauchly
A) Von Neumann is only used in embedded applications B) Harvard uses less power C) Harvard separates storage for instructions and data D) Harvard architecture uses punched cards for all logic
A) Relays and vacuum tubes B) Semiconductors and caches C) Microprocessors and ICs D) Logic gates and transistors
A) 100 kHz to 4 MHz B) 1 GHz to 4 GHz C) 1 kHz to 10 kHz D) 10 MHz to 100 MHz
A) External main memory B) Peripheral interfaces C) Graphics processing units D) ALU and registers
A) ENIAC B) EDVAC C) Manchester Mark 1 D) Atmel AVR microcontroller
A) The removal of registers B) The abandonment of logic units C) The integrated circuit D) The use of relays
A) Caches and instruction-level parallelism B) External storage C) Vacuum tube controllers D) Punched paper tape
A) EDVAC B) Manchester Baby C) ENIAC D) Harvard Mark I
A) NAND gates B) NOR gates C) XOR gates D) AND gates
A) Lunar Module 1 B) Apollo Guidance Computer C) Voyager Mission D) Gemini Spacecraft
A) System/370 B) System/380 C) System/350 D) System/390
A) PDP-7 B) PDP-8 C) PDP-11 D) PDP-10
A) A smartphone processor B) A 32-bit mainframe computer C) A portable laptop D) A graphics card
A) Ten or fewer B) Fifty C) Five hundred thousand D) A hundred or more
A) IBM B) Datapoint C) Fairchild D) Intel
A) Lee Boysel B) Federico Faggin C) Robert Noyce D) Gordon Moore
A) Mid 1980s B) Early 1970s C) Early 1960s D) Late 1970s
A) 4 B) 100 C) 24 D) 1000
A) 10 B) Roughly 1000 C) 100 D) 10,000
A) Intel 8080 B) Motorola 6800 C) Intel 4004 D) IBM 360
A) 1971 B) 1980 C) 1968 D) 1974
A) Intel 8080 B) Intel 4004 C) Intel 8086 D) MOS 6502
A) 1977 B) 1982 C) 1971 D) 1974
A) As numerous small ICs on circuit boards B) As discrete components C) As vacuum tubes D) As microprocessors
A) Cores B) Registers C) Nodes D) Modules
A) Lower clock rates B) Decreased gate parasitic capacitance C) Larger transistor size D) Increased power consumption
A) Moore's law B) Ohm's law C) Von Neumann's law D) Newton's law
A) 2000 B) 2020 C) 2016 D) 2010
A) Magnetic interference B) Electromigration C) Voltage drop D) Thermal expansion
A) Data corruption B) Overheating C) Increased clock jitter D) Subthreshold leakage
A) The pipeline process B) The memory map C) The bootstrap sequence D) The instruction cycle
A) The cache memory index B) The instruction decoder output C) The incremented value in the program counter D) The previous instruction's result
A) Quantum processing units B) Analogue circuitry C) Classic RISC pipeline D) Dynamic neural networks
A) In the cache B) In the program counter C) In a flags register D) In the opcode
A) Converting instructions into control signals B) Executing arithmetic operations C) Updating the flags register D) Retrieving an instruction from program memory
A) Memory controller B) Opcode indexer C) Address register D) Instruction pointer
A) The amount of available RAM B) The speed of the clock C) The program counter D) Instruction set architecture (ISA)
A) The flag register B) The program counter C) The immediate value D) The opcode
A) A binary decoder B) A microprogram C) A register address D) An immediate value
A) Initialization B) Execute C) Compilation D) Storage
A) Clock pulse B) Interrupt signal C) User input D) Cache miss
A) Binary decoder B) System bus C) Floating-point unit D) Arithmetic logic unit
A) The program branches B) The instruction is fetched C) Memory is cleared D) The sum appears at the output
A) Registers B) Constants C) Signals D) Operands
A) Microcontrollers B) Desktop computers C) Smartphone processors D) Server computers
A) L3 B) L2 C) L4 D) L1
A) L3 B) TLB C) L2 D) L1
A) Analog circuits B) Clockless circuits C) Asynchronous circuits D) Synchronous circuits
A) It is impossible to design B) It uses less energy C) It requires no clock signal D) The CPU must wait on its slowest elements
A) Excessive memory usage B) Electrical signal delays C) Hardware incompatibility D) Operating system crashes
A) Sega Dreamcast B) Nintendo Wii C) Xbox 360 D) PlayStation 3
A) Pentium B) PowerPC C) Intel Core D) AMULET
A) Sine wave B) Sawtooth wave C) Square wave D) Triangle wave
A) Regulate on-demand voltage supply B) Increase total number of memory locations C) Increase the word size of the CPU D) Convert binary to decimal numerals
A) 8 B) 256 C) 64 D) 32
A) Eight cycles B) Two cycles C) Four cycles D) One cycle
A) Data path width B) Bit width C) Voltage width D) Integer size
A) Less than one B) Exactly one C) Two D) Greater than one
A) Transactional memory B) Branch prediction C) Register renaming D) Out-of-order execution
A) P6 B) P4 C) P3 D) P5 Pentium
A) Speculative execution B) Branch prediction C) VLIW D) Out-of-order execution
A) MISD B) MIMD C) SISD D) SIMD
A) Shared memory processing B) Synchronous multiprocessor C) Systemic memory parallelism D) Symmetric multiprocessing
A) Manual thread migration B) Software patching C) Additional hardware D) External disk caching
A) Pipelined cache architecture B) Manual bus synchronization C) NUMA D) Single-core expansion
A) Instruction stream migration B) Discrete board architecture C) Direct memory access D) Chip-level multiprocessing
A) Direct memory access B) Multi-threading C) Symmetric multiprocessing D) Superscalar execution
A) 2 B) 4 C) 7 D) 3
A) SIMD B) SISD C) MIMD D) MISD
A) Operating system kernels B) Word processing C) Multimedia applications D) Database indexing
A) Social media networking B) Scientific research C) Web browsing D) Desktop publishing
A) Mid-1990s B) Late 2000s C) Early 1980s D) Mid-1970s
A) They were integer-only B) They lacked multimedia support C) They consumed too much power D) They were incompatible with memory
A) Basic B) MMX C) SSE D) MAX
A) MMX B) SSE C) VMX D) MAX
A) trace-cpu B) hpc-tool C) core-monitor D) perf
A) A vCPU B) A host C) A virtual server D) A cluster
A) vCPU B) vC C) VPS D) V-Core
A) Approximately 50% B) Exactly 100% C) Nearly 200% D) Less than 10%
A) Modern software is optimized for single-core only B) The memory hierarchy becomes unstable C) Inter-core communication consumes processing speed D) Physical space constraints on the integrated circuit
A) Memory leaks in the kernel B) Return-oriented programming exploits C) Low clock rate issues D) Excessive cache latency
A) A resource pool B) A host C) A vCPU D) A cluster
A) Large cloud providers B) Rated speed testing labs C) Home office environments D) Small component manufacturers
A) Only the motherboard B) Only the cloud software C) Nothing else can be overclocked D) Other components |