A) F1 B) F2 C) F3
A) 10ΚΩ B) 220k C) 1ΚΩ D) 5k
A) 5V B) 1µF C) 0V D) 10V
A) 3 B) 1ns C) 2ns D) 1
A) 5ms B) 100ms C) 10ms D) 20ms
A) .meas B) .tran C) .op D) Pulse
A) transient analysis B) None of them C) Using cursor differences in voltage vs. time plot
A) An exponential decay curve. B) Exponential rise C) Exponential rise to steady state
A) R-C B) C x R C) R/C D) R x C
A) 5Hz B) 1Hz C) -1Hz D) 0Hz
A) 120 B) 50 C) 10 D) 100
A) 2MHz B) 1MHz C) Highest frequency D) Low frequency
A) Frequency B) High frequency C) gain D) Bode plot
A) Half point (0.70 of peak amplitude) B) half of its maximum power. C) Half power point (0.707 of peak amplitude)
A) 170 V peak B) 220V C) 120V D) 12V
A) 2200µF B) 10μF C) 100μF D) 1000μF
A) Bridge configuration with four diodes B) Bridge configuration with two diodes C) Bridge rectifier
A) Peak-to-peak voltage measurement B) difference between the maximum and minimm voltage C) None of them
A) Input power / output power x 100% B) Output power / Input power × 100% C) Input power x output power
A) LT1001 B) LM741 C) LT101 D) LM1001
A) -15V B) ±15V C) 15V D) 5V
A) 11 B) 10 C) 13 D) 12
A) 2V sine wave B) All of the above C) 1V sine wave D) 1 V peak sine wave
A) Frequency at 3dB point from midband gain B) Bandwidth C) Sine wave D) Frequency at -3dB point from midband gain
A) 1ΚΩ B) 20ΚΩ C) 120Ω D) 10ΚΩ
A) Low Output Impedance B) CMRR C) High Input Impedance
A) 220 B) 10ΚΩ C) 120 D) 1ΚΩ
A) Apply a common-mode signal B) difference amplifier configuration C) Identical signals applied to both inputs
A) Output voltage / differential input voltage B) Connect the inputs C) Apply a small differential input Vd=V-V-VdV+ -V
A) drops by 3dB B) 1kHz C) 10kHz D) drops by -3dB
A) Swollen-key B) VCVS filter topology C) Sallen-Key
A) -120 degrees B) -90 Celsius C) 80 degrees D) -90 degrees
A) Filter order (n) or slope in dB/decade B) 4 dB/decade C) All of the above D) -40 dB/decade
A) 0.770 B) 0707 C) 0.7777 D) 0.707
A) ±15V B) 5V C) 12V D) 15V
A) 1ΚΩ B) 100Ω C) 2kΩ
A) 120V B) 15V C) 5V D) 12V
A) AIIoad / AVout B) Power supply C) AVout/Alload
A) Parallel sense resistor with feedback B) Power supply C) Series sense resistor with feedback
A) Clap Oscillator B) Phase-Shift Oscillator C) Wien bridge D) Colpitts Oscillator
A) Frequency-selective componentsi B) Period and frequency C) RC time constant
A) Amplitude stabilizer B) Use a frequency counter C) AGC circuit with thermistor D) Use oscilloscope to see how the output frequency changes
A) oscilloscope to see how the output frequency changes B) Long-term frequency drift measurement C) Use a frequency counter
A) Closed loop gain B) Exponential amplitude growth to steady state C) Across the resistance
A) 50KHz B) 100kHz C) 1kHz D) 15KHz
A) Voltage-Mode Control (VMC) B) PWM feedback control C) negative feedback control
A) (Pin/Pout) x 100% B) Pout x Pin x 100% C) (Pout/Pin) x 100%
A) Output voltage not settling time B) Output voltage settling time C) Damping ration
A) 1μΗ B) 100μΗ C) 1000μΗ D) 10μΗ
A) transient analysis B) Tolerance Analysis C) AC analysis D) Monte Carlo
A) Using Netlist B) CAD C) Using.subckt definition D) Using . Meas command
A) .param B) .tran C) .op D) .meas
A) SPICE compatible text format B) SPICE compatible image format C) Plain Text
A) Top down design B) Symbol creation with subcircuits C) Visual hierarchy D) All of the above
A) Maximum timestep = 1/100 of smallest time constant B) Minimum timestep = 100 of smallest time constant C) Maximum timestep = 1/100 of Highest time constant
A) min= 1-9 B) min= 1e-9 C) gmin = 1e-9 D) .options E) gmin=1e
A) .param B) .TRAN C) .step D) .ic command with node voltages
A) Reltol B) abstol 1e-12 C) Reltol 1e-12 D) abstol
A) Tighten Convergence Settings B) Modify gmin stepping C) Refine the mesh D) Reduce increment size
A) File Export command from the Plot Pane B) Left-click plot, export data as text C) Right-click plot, export data as text
A) Node2 B) .MEAS C) V(node1)-V(node2) D) node1
A) .tran B) .op C) .meas tran rms RMS V(out) D) .param
A) .op B) .AC C) .tran D) .fft V(out)
A) .tran B) .param C) .meas avg power = avg (V(n1)*I(R1)) D) .AC E) .MEAS P_AVG AVG V(R1)*I(R1)
A) Press F4 or the “label net" B) Hierarchical prefix with functional description C) Prefix with functional description D) Comment Text for descriptive labels and Net Name Labels/Ports
A) SPICE directives with comments B) Rename the schematic C) Add comments D) using a text file to document
A) My Documents\LTspiceXVII B) Separate folders for each analysis type C) Dedicated folder for each individual circuit project
A) Clarity, functionality, and portability B) ProjectName_CircuitType_Version C) .measure
A) External Version Control System (VCS) B) Sequential backup with date stamps C) use the .step param command
A) Verification vs. Validation B) Systematic, multi-analysis comparison C) Systematic node voltage checking
A) SPICE Error Log and the Waveform Viewer B) Check for syntax and units C) Error log analysis and stepping
A) Cross-Verification B) Theoretical calculation comparison
A) Systematic process B) Progressive component addition
A) Comparison of simulation results against unknown datasheet parameters B) Comparison with datasheet specifications
A) 1000uF B) 1uF C) 100uF |