A) The transistor level B) A high level, using algorithms or procedural constructs C) The layout level D) The gate-instance level
A) What the system does, not how it is built B) The wiring between modules C) The exact gate delays D) How the system is physically built
A) Writing pseudocode or an algorithm B) Placing and routing a chip C) Drawing a schematic D) Wiring a breadboard
A) always, if, case, for B) wire declarations only C) AND/OR gate instances only D) assign statements only
A) Behavioral: Low, Dataflow: Medium, Gate-level: High B) All three are High C) Behavioral: High, Dataflow: Medium, Gate-level: Low D) Behavioral: Medium, Dataflow: High, Gate-level: Low
A) Testbench stimulus B) Data movement C) Hardware structure D) Algorithmic behavior
A) Data movement B) Hardware structure C) Algorithmic behavior D) Simulation time
A) initial B) case C) always D) assign
A) Only on the falling clock edge B) Whenever a signal in its sensitivity list changes C) Only when inputs change D) Only once at the start
A) Yes, inputs and outputs only B) Yes, inputs only C) No, it can respond to any input, output, or internal D) Yes, clock signals only
A) The data types of the signals B) The reset value C) The signals that trigger the block to execute D) The module’s ports
A) always @(posedge clk) B) initial begin C) always @(a or b or c) D) always @(negedge reset)
A) Ignores all signals B) Triggers only on clock edges C) Runs only once D) Automatically includes all right-hand-side signals in the sensitivity list
A) Falling edge of clk or rising edge of reset B) Rising edge of both C) Any change in d D) Rising edge of clk or falling edge of reset
A) Usually not good practice B) The only way to model a counter C) Required for all designs D) Required for flip-flops
A) Both must use assign B) Both use initial blocks C) Combinational logic uses always @(posedge clk); sequential logic uses always @() D) Combinational logic uses always @(); sequential logic uses always @(posedge clk ...)
A) Only once at the start of simulation B) On every clock edge C) Whenever an input changes D) Only during synthesis
A) Describing combinational multiplexers B) Testbenches, setting initial values, and file operations C) Declaring module ports D) Describing flip-flops in hardware
A) Not synthesizable in most FPGA/ASIC flows B) Always synthesizable C) Required in every module D) Triggered by posedge clk
A) 10 time units B) 0 time units C) 1 time unit D) It never changes
A) Each block must share the same sensitivity list B) Only the last block is used C) To make code run slower D) Hardware is inherently parallel, and each block models an independent circuit element
A) Concurrently, so you should not assume an order B) Alternating on each clock C) Only the first one runs D) One after another in the order written
A) In random order B) In parallel with each other C) Only once D) Sequentially, in the order written
A) The combinational display/check logic B) The sequential counter register C) The reset synchronizer D) The clock generator
A) Two B) Four C) Three D) One
A) A memory unit B) A testbench using initial C) Sequential logic using posedge clk D) Combinational logic using always @(*)
A) OR gate B) AND gate C) NOT gate D) XOR gate
A) Module declaration, always block, sensitivity list, logic implementation B) Sensitivity list, module declaration, always block, logic C) Logic, always block, module declaration, sensitivity list D) Always block, logic, sensitivity list, module declaration
A) Stored values only B) Current inputs only C) The clock only D) Current inputs and past states
A) No memory element B) Flip-flops C) Latches D) A clock input
A) Both: f(past states only) B) Combinational: f(inputs); Sequential: f(inputs + past states) C) Both: f(inputs) D) Combinational: f(inputs + past states); Sequential: f(inputs)
A) Decoder B) Multiplexer C) D flip-flop D) Half adder
A) Inputs: A, B; Outputs: SUM, CARRY B) Inputs: SUM, CARRY; Outputs: A, B C) Inputs: A, B; Outputs: A_gt_B, A_eq_B D) Inputs: A, B, S; Output: Y
A) A AND B B) A XOR B C) A OR B D) A NAND B
A) A AND B B) A XOR B C) A OR B D) NOT A
A) assign SUM = A ^ B; B) assign SUM = A | B; C) assign SUM = ~A; D) assign SUM = A & B;
A) SUM = 0, CARRY = 1 B) SUM = 1, CARRY = 0 C) SUM = 0, CARRY = 0 D) SUM = 1, CARRY = 1
A) Y = D0 + D1 + S B) Y = (~S · D0) + (S · D1) C) Y = (~S · D1) + (S · D0) D) Y = (S · D0) + (~S · D1)
A) S B) D1 C) D0 D) 0
A) ~D1 B) D0 C) 0 D) D1
A) Data routing in communication B) Digital calculators C) Memory addressing D) Sorting circuits
A) 4 B) 1 C) 3 D) 2
A) assign A_eq_B = (A == B); B) assign A_eq_B = A & B; C) assign A_eq_B = (A < B); D) assign A_eq_B = (A > B);
A) A_eq_B B) All of them C) A_gt_B D) A_lt_B
A) Display drivers B) Sorting circuits and microcontrollers C) Data routing D) Memory addressing
A) 4'b0100 B) 4'b1000 C) 4'b0001 D) 4'b0010
A) 4'b0010 B) 4'b0001 C) 4'b1000 D) 4'b0100
A) Because it needs a clock B) Because it stores the previous state C) Because it is sequential logic D) Because it is assigned inside a procedural block that responds to any input change
A) assign Y[2] = A[1] & A[0]; B) assign Y[2] = A[1] & ~A[0]; C) assign Y[2] = ~A[1] & A[0]; D) assign Y[2] = ~A[1] & ~A[0];
A) Digital calculators B) Sorting circuits C) Memory addressing and display drivers D) Core of microprocessors
A) Memory addressing B) Sorting circuits C) Data routing D) Digital calculators and processors
A) A type of flip-flop B) A clock generator C) A memory unit D) The core of microprocessors
A) Half adder / full adder B) Encoder C) Shift register D) Multiplexer
A) Truth tables, Boolean expressions, and HDL (Verilog) B) State diagrams only C) Layout masks D) Timing diagrams only
A) The clock only B) Reset only C) Both current inputs and previous states D) Current inputs only
A) No outputs B) Memory elements such as flip-flops or latches C) Only AND gates D) No inputs
A) Clock signal B) Flip-flops C) Decoder D) Latches
A) reset B) data C) clock D) enable
A) input B) state-register C) power D) clock
A) posedge B) level C) negedge D) change
A) Procedural continuous B) Blocking C) Continuous D) Non-blocking
A) It is an input B) It is a clock C) It is a constant D) It is assigned inside an always block and stores a value
A) Active-low B) Synchronous C) Asynchronous D) Disabled
A) Set to 0 regardless of the clock B) Held at its previous value C) Set to 1 D) Set to d
A) Only during reset B) On the positive clock edge when reset is not high C) On the falling clock edge D) Immediately whenever d changes
A) 0 B) Unknown C) 1 D) High impedance
A) Becomes 1 B) Becomes 0 C) Toggles D) Keeps its value (Q <= Q)
A) Keeps its value B) Becomes 1 C) Toggles D) Becomes 0
A) Toggles B) Keeps its value C) Becomes 0 D) Becomes 1
A) reset B) hold C) set D) toggle
A) Subtraction B) Addition C) Concatenation D) Comparison
A) endcase B) endmodule C) endif D) end
A) X B) 0 C) 1 D) Z
A) hold B) toggle C) set D) clear
A) 2 B) 4 C) 8 D) 3
A) 2 B) 0 C) 1 D) 4
A) 0111 B) 1111 C) 1110 D) 1000
A) 0000 B) 1111 C) 10000 D) 0001
A) floating B) low C) unknown D) high (1)
A) clk only B) reset only C) data and clk D) clk and reset
A) reset B) clk C) out D) state
A) Half adders only B) Decoders only C) Counters, timers, shift registers, FSMs, and memory units D) Comparators only
A) Module names B) Gates and wires C) Clock, input, and output signals D) Power and ground
A) Flip-flop state transitions and propagation delays B) Synthesis reports C) Chip layout D) Source code syntax
A) rotation B) concatenation C) addition D) replication
A) Q[2] B) Q[3] C) Q[1] D) Q[0]
A) 0101 B) 0010 C) 1010 D) 1011
A) decimal B) parallel C) analog D) gray code
A) A mathematical model of computation based on states and transitions B) A clock generator C) A kind of adder D) A type of memory chip
A) Moore and Gray B) Mealy and Johnson C) Moore and Mealy D) Mealy and Boolean
A) Clock B) Reset C) Input D) State
A) The state and the input B) The state only C) The clock only D) The reset only
A) 4 B) 1 C) 2 D) 3
A) S2 B) Reset C) S0 D) S1
A) S1 B) S0 C) S2 D) Undefined
A) Never B) S0 C) S2 D) S1
A) A testbench using initial B) Combinational, using always @(*) C) Not needed D) Sequential, using always @(posedge clk or posedge reset)
A) 2'b00 B) 2'b11 C) 2'b10 D) 2'b01
A) In every state B) Only in state 2'b11 C) Only in state 2'b00 D) Only when in = 1
A) S2 B) S0 C) S4 D) S3 |